About Me
With a major in Computer Architecture, I am First Stage Researcher (R1) in the area of Digital Design and my skill set is equally suitable for allied areas of research such as Hardware for Machine Learning Applications, High Performance Reconfigurable Computing, Fixed-point versus Floating-point Systems, Digital Signal Processors, Machine Learning and Hardware Security. I am open to disciplinary research and industrial collaboration.
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Research Publication
1. Ijaz, Qaiser and Bourennane, El-Bay. 2023. “An Optimized Topology for High-Performance Reconfigurable Computing. Part I: Analysis of 2D and 3D NoC Topologies.” IEEE 23. https://doi.org/10.1109/ICEST56843.2023.10138834
2. Ijaz, Qaiser and Kidane, Hiliwi Leake and Bourennane, El-Bay and Ochoa-Ruiz, Gilberto. 2023. “Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications.” MDPI AG 14. https://doi.org/10.3390/mi14101913
3. Ijaz, Qaiser and Bourennane, El-Bay. 2021. “Wireless versus Wired Network-on-Chip to Enable the Multi- Tenant Multi-FPGAs in Cloud.” IEEE 21. https://doi.org/10.1109/IEMTRONICS52119.2021.9422654
4. Ijaz, Qaiser and Bourennane, El-Bay. 2020. “Wireless NoC for Inter-FPGA Communication: Theoretical Case for Future Datacenters.” IEEE 20. https://doi.org/10.1109/INMIC50486.2020.9318048
5. Ijaz, Qaiser and Bourennane, El-Bay and Bashir, Ali Kashif and Asghar, Hira. 2020. “Revisiting the High-Performance Reconfigurable Computing for Future Datacenters.” MDPI AG 12. https://doi.org/10.3390/fi12040064
6. Ijaz, Qaiser and Asghar, Hira and Ahsan, Ali. 2016. “Exploratory study to investigate the correlation and contrast between ISO 9001 and CMMI framework: Context of software quality management.” IEEE 16. https://doi.org/10.1109/INTECH.2016.7845114
7. Ahmad, Usman and Ijaz, Qaiser and Husnain, Anees ul. 2015. “Stability Analysis of Coupled Van Der Pol’s Oscillator.” IEEE 15. https://doi.org/10.1109/FIT.2015.16
8. Arshad, Sahar and Ismail, Muhammad and Ahmad, Usman and Husnain, Anees ul and Ijaz, Qaiser. 2014. “Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design.” Wiley 2014. https://doi.org/10.1155/2014/406416